https://www.anandtech.com/show/15839/electromigration-amd-ryzen-current-boosting-wont-kill-your-cpu This article is proof of there doesn't simply exist some startling misconceptions amongst the wider audience and community consisting of enthusiastic engineers and consumers considering that it was written to accommodate the same who dogmatically believe that there it is engineeringly feasible to correlate publicly marketed processor specifications such as PPT, TDC & EDT with a scientific concept like electromigration. What cannot be forgiven is the grossly inaccurate assumption that poor power factor as a result lacklustre motherboard design that also is assumed to be consistent across motherboard vendors and CPU vendor engineering teams when finalising the TDP values for their respective power states. If this is representative of the present state of communication between CPU vendor marketing teams and the consumer audience, then I wonder how long it might take the enthusiast community to actually realise the difference in idealogy between Intel and AMD, where AMD resorts to a somewhat engineeringly unintuitive chiplet design strategy BUT compensates by implementing an incredibly optimised voltage sub-domain ISA for their chiplets alone while Intel sticks to the tried-and-tested monolithic design while opting to defer from publicly marketing majority of its voltage sub-domain ISA optimisations for its SRAM core resulting in smaller but faster SRAM caches. It should be noted that the same faster SRAM cache on a larger node that Intel sells, all the while remaining competitive with AMD CPUs that created on a node that is considered to be a generation ahead, is very telling of the glaring differences in engineering intuition between the actual engineers and the enthusiast consumers. Although, for this to happen the enthusiast community has to first acknowledge that CPU vendors have long since been designing their CPUs with optimised cores and caches that safely outpace improvements in the evolution of data selector prefetches of DRAM technology.